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P4C174 HIGH SPEED 8K x 8 CACHE TAG STATIC RAM
FEATURES
High Speed Address-To-Match - 8 ns Maximum Access Time High-Speed Read-Access Time - 8/10/12/15/20/25 ns (Commercial) - 15/20/25 ns (Military) Open Drain MATCH Output Reset Function 8-Bit Tag Comparison Logic Automatic Powerdown During Long Cycles Data Retention at 2V for Battery Backup Operation Advanced CMOS Technology Low Power Operation Package Styles Available -- 28 Pin 300 mil DIP -- 28 Pin 300 mil Plastic SOJ Single Power Supply -- 5V10%
DESCRIPTION
The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8. The CMOS memory has equal access and cycle times. Inputs are fully TTL-compatible. The cache tag RAMs operate from a single 5V10% power supply. An 8-bit data comparator with a MATCH output is included for use as an address tag comparator in high speed cache applications. The reset function provides the capability to reset all memory locations to a LOW level. The MATCH output of the P4C174 reflects the comparison result between the 8-bit data on the I/O pins and the addressed memory location. 8K Cache lines can be mapped into 1M-Byte address spaces by comparing 20 address bits organized as 13-line address bits and 7page address bits. Low power operation of the P4C174 is enhanced by automatic powerdown when the memory is deselected or during long cycle times. Also, data retention is maintained down to VCC = 2.0. Typical battery backup applications consume only 30 W at VCC = 3.0V.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (C5, P5), SOJ (J5)
Document # SRAM118 REV C 1 Revised August 2006
P4C174
MAXIMUM RATINGS(1)
Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value -0.5 to +7 -0.5 to VCC +0.5 -55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -55 to +125 -65 to +150 1.0 50 Unit C C W mA
VTERM TA
V C
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade(2) Commercial Commercial Ambient Temperature 0C to +70C 0C to +70C GND 0V 0V VCC 5.0V 10% 5.0V 10%
CAPACITANCES(4)
VCC = 5.0V, TA = 25C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions Typ. Unit VIN = 0V VOUT = 0V 5 7 pF pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2) Symbol VIH VIL VHC VLC VCD VOL VOH ILI ILO ISB Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage VCC = Min., IIN = 18 mA Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current Output Leakage Current IOL = +8 mA, VCC = Min. IOH = -4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., CE = VIH, VOUT = GND to VCC Com'l. Mil. Com'l. Mil. 2.4 -5 -10 -5 -10 ___ ___ ___ ___ +5 +10 +5 +10 25 40 5 25 mA Test Conditions P4C174 Min Max 2.2 -0.5(3) -0.5(3) VCC +0.5 0.8 0.2 -1.2 0.4 Unit V V V V V V V A A
VCC -0.2 VCC +0.5
CE VIH Com'l. Standby Power Supply Mil. Current (TTL Input Levels) VCC = Max ., f = Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE VHC VCC = Max., f = 0, Outputs Open VIN VLC or VIN VHC Com'l. Mil.
ISB1
mA
n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested.
Document # SRAM118 REV C
Page 2 of 12
P4C174
DATA RETENTION CHARACTERISTICS (P4C174 Military Temperature Only)
Symbol VDR ICCDR tCDR tR
*TA = +25C tRC = Read Cycle Time
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Test Conditons
Min 2.0
Typ.* VCC = 2.0V 3.0V
Max VCC = 2.0V 3.0V
Unit V
CE VCC -0.2V, VIN VCC -0.2V or VIN 0.2V 0 tRC
10
15
600
900
A ns ns
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol ICC Parameter Dynamic Operating Current* Temperature Range Commercial Military -8 200 -10 180 -12 170 170 -15 -20 155 160 -25 150 155 Unit mA mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
Document # SRAM118 REV C
Page 3 of 12
P4C174
AC CHARACTERISTICS--READ CYCLE
(VCC = 5V 10%, All Temperature Ranges)(2)
Symbol tRC tAA tOH tAC tLZ tHZ tOE tOLZ tOHZ tPU
Parameter Read Cycle Time Address Access Time Address Change to Output Change Chip Enable LOW to Output Valid Chip Enable LOW to Output LOW-Z (1) Chip Enable HIGH to Output HIGH -Z (1) Output Enable LOW to Output Valid Output Enable LOW to Output LOW-Z (1) Output Enable HIGH to Output HIGH -Z (1) Chip Enable LOW or Address Change to Powerup Powerup to Powerdown
-8 Min Max 8 8 3 8 3 5 5 0 5 0 0 0 3 3 10
-10 12 10 3 10 3 5 6 0 5 0
-12 Max 12 3 12 3 5 6 0 5 0 15
-15 Min Max 15 3 15 3 8 8 0 5 0 20
-20 Min 25 20 3 20 3 8 10 0 8 0
-25
Min Max Min
Max Min Max 25
Unit ns ns ns
25
ns ns
10 12
ns ns ns
10
ns ns
tpUPD
20
20
20
20
20
25
ns
Note: 1. Transition is measured 200 mV from steady state voltage with Output Load B.
READ CYCLE NO. 1 (OE CONTROLLED)(2, 3) OE
Document # SRAM118 REV C
Page 4 of 12
P4C174
READ CYCLE NO. 2 (ADDRESS CONTROLLED)(2)
READ CYCLE NO. 3 (CE CONTROLLED)(2, 3) CE
Notes: 1. Transition is measured 200 mV from steady state voltage with Output Load B. This parameter is sampled, not 100% tested. 2. CE is LOW, OE is LOW, WE is HIGH for READ cycle. CE or WE must be HIGH during address transitions. 3. All address lines are valid no later than the transition of CE to LOW. 4. READ cycle time is measured from the last valid address to the first transitioning address. 5. Powerup occurs as a result of any of the following conditions: a) Falling edge of CE. b) Falling edge of WE (CE active). c) Any address line transition (CE active). d) Any Data line transition (CE and WE active). This device automatically powers down after TPUPD has elapsed from any of the prior conditions. Power dissipation is therefore a function of cycle rate, not CE pulse width. 6. CE is LOW, WE is LOW for WRITE cycle. CE or WE must be HIGH during address transitions. 7. WRITE cycle time is measured from the last valid address to the first transitioning address. 8. OE is LOW for this WRITE cycle to show TWZ and TOW.
Document # SRAM118 REV C
Page 5 of 12
P4C174
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V 10%, 0C to +70C) Symbol tWC tCW tAS tAW tAH tWP tDW tDH tOW tWZ Parameter Write Cycle Time Chip Enable LOW to End of Write Address Valid to Beginning of Write Address Valid to End of Write End of Write to Address Change Write Pulse Width Data Valid to End of Write End of Write to Data Change Write Enable HIGH to Output LOW-Z (1) Write Enable LOW to Output HIGH-Z (1) -8 8 7 0 7 0 7 6 0 0 4 -10 10 9 0 9 0 9 6 0 0 4 -12 12 10 0 10 0 10 6 0 0 4 -15 15 12 0 12 0 12 7 0 0 5 -20 20 15 0 15 0 15 10 0 0 7 -25 20 15 0 15 0 15 10 0 0 7 Min Max Min Max Min Max Min Max Min Max Min Max Unit ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE NO. 1 (WE CONTROLLED)(6) WE
CE WRITE CYCLE NO. 2 (CE CONTROLLED)(6)
Document # SRAM118 REV C
Page 6 of 12
P4C174
AC CHARACTERISTICS - MATCH CYCLE
(VCC = 5.0V 10%, 0C to +70C) Symbol tMC tADM tADMH tCEM tCEMHI tOEMHI tWEMHI tDAM tDAMH Parameter Match Cycle Time Address Valid to MATCH Valid Address Change to MATCH Change Chip Enable LOW to MATCH Valid Chip Enable HIGH to MATCH HIGH Output Enable LOW to MATCH HIGH Write Enable LOW to MATCH HIGH Data Valid to MATCH Valid Data Change to MATCH Change 0 -8 8 8 3 7 7 7 7 7 0 3 8 8 9 9 9 0 10 10 3 8 8 10 10 10 0 -10 12 12 3 10 10 12 12 13 0 -12 15 15 3 10 10 15 15 15 0 -15 20 20 3 15 15 20 20 15 -20 25 25 -25 Min Max Min Max Min Max Min Max Min Max Min Max Unit ns ns ns ns ns ns ns ns ns
MATCH TIMING
Document # SRAM118 REV C
Page 7 of 12
P4C174
AC CHARACTERISTICS - RESET CYCLE
(VCC = 5.0V 10%, 0C to +70C) Symbol tRRC tRP tRPU tRPD tRMHI tRIX tRIR tPUR Parameter Reset Cycle Time Reset Pulse Width Reset LOW to Powerup Reset LOW to Powerdown Reset LOW to MATCH HIGH Reset LOW to Inputs Ignored Reset LOW to inputs Recognized Powerup to RESET LOW 0 0 35 8 10 -8 35 8 0 35 8 0 0 40 12 -10 40 10 0 40 10 0 0 45 15 -12 45 12 0 45 10 0 0 50 20 -15 50 12 0 50 12 0 0 50 25 -20 50 15 0 50 15 0 0 60 -25 60 15 0 60 20 Min Max Min Max Min Max Min Max Min Max Min Max Unit ns ns ns ns ns ns ns ns
RESET TIMING
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Load GND to 3.0V < 3ns 1.5V Outputs Loads A, B & C
TRUTH TABLE
Mode Standby Read Write CE H L L WE X H L Output High Z DOUT High Z Power Standby Active Active
Output Timing Reference Level 1.5V
Document # SRAM118 REV C
Page 8 of 12
P4C174
OUTPUT LOAD A
OUTPUT LOAD B
OUTPUT LOAD C
ORDERING INFORMATION
SELECTION GUIDE
The P4C174 is available in the following temperature, speed and package options.
Temperature Range Commercial Miliitary Temperature Military Processed* Package Plastic DIP Plastic SOJ Side Brazed DIP Side Brazed DIP Speed 8 -8PC -8JC N/A N/A 10 -10PC -10JC N/A N/A 12 -15PC -15JC N/A N/A 15 -15PC -15JC -15CM -15CMB 20 -20PC -20JC -20CM -20CMB 25 -25PC -25JC -25CM -25CMB
* Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available
Document # SRAM118 REV C
Page 9 of 12
P4C174
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2
C5
28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 -
SIDE BRAZED DUAL IN-LINE PACKAGE
Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q
J5
28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 -
SOJ SMALL OUTLINE IC PACKAGE
Document # SRAM118 REV C
Page 10 of 12
P4C174
Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L
P5
28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0 15
PLASTIC DUAL IN-LINE PACKAGE
Document # SRAM118 REV C
Page 11 of 12
P4C174
REVISIONS
DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B C ISSUE DATE 1997 Oct-05 Nov-05 Aug-06 SRAM118
P4C174 HIGH SPEED 8Kx8 CACHE TAG STATIC RAM
ORIG. OF CHANGE DAB JDB JDB JDB
DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Corrected error in Selection Guide Updated SOJ package information
Document # SRAM118 REV C
Page 12 of 12

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